1. Field of the Invention
In high bit rate digital mobile communication, waveform distortion produced due to frequency selective fading causes severe performance degradation in the transmission system. The present invention relates to an adaptive equalizer and an adaptive diversity equalizer both used for the purpose of reducing the performance degradation in the transmission system.
2. Description of the Prior Art
A structure and operation of a conventional adaptive equalizer will first be described below. As one of baseband adaptive equalizers capable of tracking a time-varying channel observed in mobile communication and effecting its initialization in accordance with a short-time training process, there is known such a decision feedback adaptive equalizer as described in, e.g., an article: "Performance of a Decision Feedback Equalizer under Frequency Selective Fading in Land Mobile Communications" by Nakajima and Sampei, published in the Transaction of IEICE, Vol. J72-B-II. No. 10, pp 513-523, October 1989. Further, as one constructed for the purpose of improving characteristics in a decision feedback adaptive equalizer, reducing the amount or quantity of calculation and reducing the power to be consumed by a receiver including an equalizer, there is known one such as an automatic equalizer disclosed in Japanese Patent Application Laid-Open Publication No. 3-244220, an equalizer disclosed in Japanese Patent Application Laid-Open Publication No. 3-242015, a digital communication control device disclosed in Japanese Patent Application Laid-Open Publication No. 4-77019.
FIG. 15 is a block diagram showing a decision feedback adaptive equalizer described in the above references. In FIG. 15, reference numeral 1 indicates a transversal filter of a feedforward section (FF section) in which the interval between taps is a predetermined delay time interval Tp second and the number of the taps is an L, reference numeral 2 indicates a transversal filter of a feedback section (FB section) which the interval between taps is a given delay time interval T second and the number of taps is (M-L), reference numeral 3 indicates an adder for adding data outputted from the FF section 1 and data outputted from the FB section 2 together, reference numeral 4 indicates a decision circuit for identifying and performing hard decision on an output signal series of the adder 3 for each T seconds, reference numeral 5 indicates an adder for determining the difference between an output of the adder 3 and a signal series outputted from the decision circuit 4 or a known signal series, reference numeral 6 indicates a tap coefficient update circuit for setting tap coefficients for the FF section 1 and the FB section 2 for each T seconds, reference numeral 7 indicates a switching circuit for switching a signal series inputted to the FB section 2 to the output signal series or the known signal series of the decision circuit 4, reference numeral 8 indicates a received-signal input terminal of the decision feedback adaptive equalizer, reference numeral 9 denotes a reference-signal series input terminal, and reference numeral 10 denotes an output signal terminal of the decision feedback adaptive equalizer.
FIG. 16 is a view for describing one example of a burst format of a signal employed in mobile communication or the like. Designated at numeral 11 is a unique word (hereinafter called a "UW") used to effect the training of the adaptive equalizer and provide frame synchronization. Reference numeral 12 indicates random data.
FIG. 17 is a block diagram showing the conventional equalizer disclosed in Japanese Patent Application Laid-Open Publication No. 3-244220. In the figure, reference numeral 13 indicates a symbol spaced automatic equalizer, reference numeral 14 indicates a fractionally spaced automatic equalizer, reference numeral 15 indicates an output selector switch, and reference numeral 16 indicates a switch controller for controlling the output selector switch 15.
FIG. 18 is a block diagram showing the conventional equalizer disclosed in Japanese Patent Application Laid-Open Publication No. 3-242015. In the drawing, reference numeral 17 indicates a received-signal memory for storing reception baseband signals of I and Q channels therein. Reference numeral 18 indicates an equalizing processor for reading a reception signal corresponding to UW11 or random data 12 from the received-signal memory 17 and effecting an equalizing process on it. Reference numeral 19 denotes an equalized-output memory for storing an equalized output data corresponding to a predetermined amount therein and outputting it as received data therefrom. Reference numeral 20 indicates a controller for controlling the received-signal memory 17, the equalizing processor 18 and the equalized-output memory 19.
FIG. 20 is a block diagram showing the digital communication control device including an equalizer, which has been disclosed in Japanese Patent Application Laid-Open Publication No. 4-77019. In the drawing, reference numeral 21 indicates an input signal distributor for dividing an SI corresponding to a reception signal into a signal S1 and a signal S2, reference numeral 22 indicates a delay circuit for delaying the first signal S1 outputted from the input signal distributor 21 by a time interval longer than a period corresponding to the UW11, reference numeral 23 indicates an adaptive automatic equalizer, reference numeral 24 indicates a changeover switch for providing connection and disconnection between the output of the delay circuit 22 and the adaptive automatic equalizer 23, reference numeral 25 indicates a differential detector, a delay circuit for enabling data excluding UW, of demodulated data outputted from the differential detector 25 to be delayed by a time interval required to effect an equalizing process on the data by the adaptive automatic equalizer 23, reference numeral 27 indicates a bit error rate measuring device for comparing UW demodulated by the differential detector 25 with the known UW and calculating or counting bit error rates which exist during a UW period from the result of comparison, reference numeral 28 indicates a first demodulator made up of the delay circuit 22, the changeover switch 24 and the adaptive automatic equalizer 23, reference numeral 29 indicates a second demodulator made up of the differential detector 25 and the delay circuit 26, and reference numeral 30 indicates a changeover switch for selecting either one of outputs produced from the first and second demodulators 28 and 29 based on a control signal outputted from the code error rate measuring device 27.
Operation of the conventional equalizer will next be described.
The decision feedback adaptive equalizer shown in FIG. 15 estimates channel characteristics with respect to a received signal converted into a baseband signal by a demodulator, using the UW11 shown in FIG. 16, which corresponds to the head of each burst to thereby converge tap coefficients (training mode). At this time, each of the input signal series in the FB section 2 and the input signal series in the adder 5 is a reference signal series defined based on the known signal series of the UW11 as data free of errors in decision.
Next, the decision feedback adaptive equalizer effects an equalizing process on random data 12 (tracking mode). At this time, the decision circuit 4 identifies and performs a hard decision on the output signal series for each T seconds. Each of the input signal series in the FB section 2 and the input signal series in the adder 5 is brought to the output signal series of the decision circuit 4.
The tap coefficient update circuit 6 updates tap coefficients for the FF and FB sections 1 and 2 for each symbol in accordance with tap-coefficient update algorithms such as Kalman filter algorithms (RLS algorithms) using the input signal series of the decision feedback adaptive equalizer and the output data sequence of the adder 5 defined based on the reference data sequence that are determined by the known data sequence or the output data sequence of the decision circuit 4.
The tap-coefficient update algorithms will now be described in brief by the following example of the Kalman filter algorithms (RLS algorithms).
A signal vector inputted to an equalizer at a time t=nT (where n=0, 1, 2, . . . ) is represented as X.sub.M (n), a tap coefficient is represented as C.sub.M (n), an equalizer output is represented as I(n), a desired output is represented as d(n) and an error signal is represented as e(n).
Now, X.sub.M (n), C.sub.M (n), I(n) and d(n) are complex numbers indicative of in-phase and quadrature channels. Assuming that the number of taps in the FF section 1 of the decision feedback adaptive equalizer is represented as L and the total number of taps is represented as M, the relationships between these are given by the following equations: EQU X.sub.M (n)=[y.sub.1 *(n), y.sub.2 *(n), . . . , y.sub.L *(n), d.sub.1 *(n), d.sub.2 *(n), . . . , d.sub.M-L *(n)]* (1) EQU C.sub.M (n)=[C.sub.1 *(n), C.sub.2 *(n), . . . , C.sub.M *(n)]*(2) EQU I(n)=C.sub.M *(n-1)X.sub.M (n) (3) EQU e(n/n-1)=d(n)-I(n)=d(n)-C.sub.M *(n-1)X.sub.M (n) (4)
where * represents a complex conjugate transposed matrix (or vector), y(n) represents an input signal to be received by the FF section, and d(n) represents a signal inputted to the FB section. Under the training mode, d(n) is an output signal series obtained by performing a hard decision on the result of the equation 3 by the decision circuit 4, while under the tracking mode d(n) is the known data sequence.
Further, the error signal e(n) represents the output of the adder 5. The tap coefficient C.sub.M (n) that minimizes a cost function .epsilon. given by the following equation, is a desired value: ##EQU1## where .lambda. represents a forgetting factor (0&lt;.lambda..ltoreq.1). C.sub.M (n), which minimizes the equation 5, is as follows: ##EQU2## where .delta. represents a positive constant. ##EQU3##
The algorithm for recursively obtaining C.sub.M (n) at time t=Nt from C.sub.M (n-1) and P(n-1) at time t=(n-1)T is as follows: EQU K(n)=P(n-1)X.sub.M (n)/[.lambda.+X.sub.M *(n)P(n-1)X.sub.M (n)](9) EQU P(n)=P(n-1)-K(n)X.sub.M *(n)P(n-1) (10) EQU C.sub.M (n)=C.sub.M (n-1)+K(n)e*(n/n-1) (11) EQU P(0)=.delta..sup.-1 I, C.sub.M (0)=0 (12)
where K(n) represents a Kalman gain, P(n) represents a predicted-error covariance matrix of tap coefficients, and I represents a unit matrix.
Incidentally, the tap-coefficient update algorithms have been described in detail in the reference: "Introduction to Adaptive Filter" written by S. Hekin and translated by K. Takebe, Chapter 5, Gendai Kogakusha (1987) or the reference: "DIGITAL COMMUNICATION" by J. G. PROAKIS, Chapters 6, 8, McGRAW-HILL (1983).
Operation of the equalizer shown in FIG. 17 will now be described. Now, the symbol spaced automatic equalizer 13 is constructed in such a manner that the interval between the taps in the FF section employed in the decision feedback adaptive equalizer shown in FIG. 15 is set to one symbol, i.e., T seconds. The fractionally spaced automatic equalizer 14 is also constructed in such a way that the interval between the taps in the FF section employed in the decision feedback adaptive equalizer shown in FIG. 15 is set to (M/N) symbols, i.e., (M/N)T seconds (where M and N: integer and M&lt;N). Both the symbol spaced automatic equalizer 13 and the fractionally spaced automatic equalizer 14 may be used as linear equalizers each free of a decision feedback unit.
A reception signal is first supplied to each of the symbol spaced automatic equalizer 13 and the fractionally spaced automatic equalizer 14. The outputs of the symbol spaced automatic equalizer 13 and the fractionally spaced automatic equalizer 14 are selected by and outputted from the output selector switch 15. When a multipath delay time interval is long as in the case where a receiver is located far away from a transmitter, for example, that is when the difference in time between a direct wave and a delayed wave is large, the switch controller 16 sets up the output selector switch 15 so that it selects the output of the symbol spaced automatic equalizer 13. On the other hand, when the multipath delay time interval is short like the case where the receiver is located nearby the transmitter, for example, the switch controller 16 controls the output selector switch 15 so that it selects the output of the fractionally spaced automatic equalizer 14. As specific methods of effecting changeover control on the output selector switch 15, there are known those disclosed in Japanese Patent Application Laid-Open Publication No. 3-244220, such as a method of checking the amplitude of eyepatterns of the output of the adder 3 in both the symbol spaced automatic equalizer 23 and fractionally spaced automatic equalizer 14 and selecting the equalizer whose amplitude of the eyepatterns is larger than the other, a method of calculating the variance of amplitude of eyepatterns of both equalizers and selecting the equalizer whose variance of amplitude of the eyepatterns is smaller than the other, a method of providing a means for effecting a forward error correction on the outputs of both equalizers, comparing the degrees of correction effected on their outputs and effecting changeover control on the output selector switch 15 based on the result of comparison, etc.
Operation of the equalizer shown in FIG. 18 will now be described with reference to FIG. 19. The equalizing processor 18 effects an equalizing process on the random data 12 based on tap coefficients set in accordance with a process effected on the UW11 but temporarily stops the equalizing process in the course of one burst signal. The controller 20 assumes that a data sequence subjected to the equalizing process and stored in the equalized-output memory 19 is correct, regards the data sequence as a known data sequence used for re-training and causes the equalizing processor to effect retraining. That is, a reading pointer of the received-signal memory 17 is returned forward by a length of the training sequence. The equalizing processor 18 effects a re-training process using a part of the random data read from the received-signal memory 17, based on the known data sequence read from the equalized-output memory 19. The equalizing processor 18 is reset at the start of the re-training period. However, the already-set tap coefficients are held without returning to an initial condition. As a result, the tap coefficients set by the re-training can be converged at a high speed. The timing for temporarily stopping the equalizing process in the course of the one burst signal is decided based on the relationship between the length of the UW, a required signal processing speed and a tracking property. In the same manner as described above, the re-training process is repeated up to the end of the one burst signal. Thus, although the equalizer has been reset to effect the training process on only the beginning of the one burst signal in the conventional apparatus, the tracking property can be improved by periodically resetting the equalizer even during the stage of effecting the equalizing process on the random data and resetting the tap coefficients.
Operation of the digital communication control device shown in FIG. 20 will now be described. A baseband input signal SI has already been converted to the baseband digital data and are divided into two signals each having the same content by the input signal distributor 21. Two divided signals are represented as S1 and S2 respectively. The first signal S1 is inputted to the delay circuit 22 and the second signal S2 is inputted to the differential detector 25. The differential detector 25 effects the following predetermined operation on the signal to be demodulated using a differential detection scheme regarding the signal detected one symbol previous as a reference phase signal. That is, when the difference in phase between the signal and the previous signal is .pi./2 or less, "0" is outputted. On the other hand, when the phase difference is .pi./2 or more, "1" is outputted. Thereafter, received signals each corresponding to the UW11 located at the top of each burst are successively demodulated.
On the other hand, only UW11 of signals outputted from the differential detector 25 is inputted to the bit error rate measuring device 27, so that a bit error rate is measured. Further, data excluding a UW signal of the signals outputted from the differential detector 25 is inputted to the delay circuit 26.
The first signal S1 inputted to the delay circuit 22 is delayed by a time interval required to demodulate the UW11 of the corresponding signal by the differential detector 25 of the second demodulator 29 and complete the measurement of the bit error rate, and is thereafter inputted to the adaptive automatic equalizer 23 through the changeover switch 24 controlled by a flag decided depending on a desired threshold value by the bit error rate measuring device 27. Whenever the flag is reset, the signal S1 is not inputted to the adaptive automatic equalizer 23 and the adaptive automatic equalizer 23 is not active.
Further, a signal excluding the UW, which has been inputted to the delay circuit 26 from the differential detector 25 is delayed by a time interval required to cause the signal outputted from the delay circuit 22 to pass through the changeover switch 24 so that the signal is inputted to the adaptive automatic equalizer 23 and to complete an equalizing process on the signal.
Thus, the signals obtained by demodulating the signals having the same contents appear at an output terminal of the first demodulator 28 and an output terminal of the second demodulator 29 at the same time. The demodulated results are selectively outputted via the switch 30 controlled by the flag.
As described above, the state of a multipath can be taken and the demodulator having the adaptive automatic equalizer can be selected for each burst unit by monitoring the training signal demodulated by the demodulator having no adaptive automatic equalizer. As a result, communications can be made without degradation of the reliability (speech quality or the like) of information on the receiver. Further, the operation of the automatic equalizer whose consumption power is very high can be controlled. As a result, the power consumption in each demodulator can be greatly reduced. Further, the limited capacity of a power supply, which is employed in a telephone set mounted on and carried in a mobile, can be effectively used.
A conventional adaptive diversity equalizer will next be described. As one of adaptive diversity equalizers wherein equalizers and diversity reception have been combined, there is known one which has been described in the reference: "BER Performance of Selection Diversity with Adaptive Equalizers for Mobile Radio" by Higashi and Suzuki, 1990 Autumn Natl. Conv. Rec., IEICE, B-279, for example.
FIG. 21 is a block diagram showing the adaptive diversity equalizer disclosed in the above reference. In the drawing, reference numerals 101, 102 respectively indicate antennas, reference numeral 103 indicates a detector circuit a for detecting a receive signal outputted from the antenna 101 and converting it into a baseband signal, reference numeral 104 indicates a detector circuit for detecting a receive signal outputted from the antenna 102 and converting it into a baseband signal, reference numeral 105 indicates a decision feedback adaptive equalizer for equalizing the output of the detector circuit 103, reference numeral 106 indicates a decision feedback adaptive equalizer for equalizing the output of the detector circuit 104, reference numeral 107 indicates a comparator for comparing equalized errors produced from the decision feedback adaptive equalizers 105, 106, and reference numeral 108 indicates a selecting circuit for selecting either the output of the decision feedback adaptive equalizers 105 and 106 in response to a signal outputted from the comparator 107 and setting the selected output as a final equalized output.
Operation of the conventional adaptive diversity equalizer will next be described.
In the adaptive diversity equalizer shown in FIG. 21, the input signals outputted from the antennas 101 and 102 are respectively converted into the baseband signals by the detector circuit 103 and 104. The output signal of the detector circuit 103 is inputted to the decision feedback adaptive equalizer 105 and the output signal of the detector circuit 104 is inputted to the decision feedback adaptive equalizer 106. Each of the decision feedback adaptive equalizer 105 and the decision feedback adaptive equalizer 106 estimates characteristics of a channel using the UW11 which is located in each burst head shown in FIG. 16, as described in the paragraphs of the operation of the equalizer shown in FIG. 15 and converge tap coefficients. Next, each of the decision feedback adaptive equalizer 105 and the decision feedback adaptive equalizer 106 equalizes random data 12 and calculates the mean value of the equalized errors. Each of the equalizers outputs the result of calculation to the comparator 107. The comparator 107 compares the mean value of the equalized errors produced from the decision feedback adaptive equalizer 105 and the mean of the equalized errors produced from the decision feedback adaptive equalizer 106 and outputs a signal to the selecting circuit 108 indicating that one of the two mean values, which is smaller than the other, is to be selected. In response to the output of the comparator 107, the selecting circuit 108 outputs either the output of the decision feedback adaptive equalizer 105 or the output of the decision feedback adaptive equalizer 106 as a final equalized output.